Featured essay
The Workflow Layer: Where AI Can Change Semiconductor Engineering
The bottleneck is not generating more engineering output. It is shortening the path from new evidence to a decision engineers can trust.
Semiconductors × AI agents
Software got its agents.Silicon hasn’t.
Postdoctoral Researcher The Chinese University of Hong Kong
- Ph.D. Microelectronics Purdue
- 300-mm fab tape-out HiSilicon
- Agentic workflows CUHK
Background
From semiconductor devices to agentic workflows
I am building systems to shorten semiconductor engineering cycles without weakening engineering judgment.
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Where I came from
I spent more than 5,000 hours in Purdue cleanrooms, fabricating oxide-semiconductor transistors and learning the full loop from process design to electrical measurement. At HiSilicon, I took a vertical gate-all-around device architecture through a 300-mm production fab, working from simulation and process integration to silicon data.
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Why I moved
Semiconductor development still depends on manual loops: triaging test data, recalibrating models as new silicon arrives, and reconstructing decisions that were never captured. The work is repetitive, but it still consumes expert time and slows the next iteration. I moved toward AI because agents can take on the repeatable execution while engineers retain judgment, review, and accountability.
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What I build now
At CUHK, I build and evaluate agent systems for semiconductor engineering, starting with compact modeling. I focus on the tools, physical constraints, and evidence trails that keep an agent’s work controlled and auditable. The goal is to automate repeatable parts of semiconductor workflows and shorten engineering cycles without giving up physical rigor or engineering control.
Where to start
The argument, the work, and the record
Research
What it takes for an agent to touch a device model
How agents can perform device-modeling tasks within clear physical boundaries, leave an auditable decision trail, and turn reviewed experience into reusable engineering knowledge.
Publications
Device physics, fabrication, and reliability
Experimental transistors for future logic and memory, from new device architectures and record drain currents to the reliability physics that determines whether they remain stable.
Knowledge map
From agents to atoms
What I know, and what I don’t.
- Unexplored
- Aware
- Working
- Expert
AI
AI applications and agents
- Prompting and context engineering : Expert
- Retrieval and RAG : Expert
- Tool use and function calling : Expert
- Agent orchestration : Expert
- Multimodal applications : Working
- Evaluation and benchmarking : Working
- Guardrails and safety : Working
- Deployment and observability : Working
Model training and inference
- Deep learning foundations : Expert
- Transformer architecture : Expert
- Training dynamics and optimization : Working
- Pre-training and scaling laws : Aware
- Fine-tuning and PEFT : Working
- RL and post-training : Aware
- Distributed training : Aware
- Quantization and compression : Aware
- Inference and serving : Aware
Data
Data systems and storage
- Data models and schema : Aware
- Storage engines and page layout : Aware
- Indexing and access methods : Aware
- Query execution : Aware
- Query optimization : Unexplored
- Transactions and concurrency control : Aware
- Logging and recovery : Aware
- Analytical and columnar engines : Unexplored
- Vector search and embeddings : Working
Data platform and distribution
- Distributed storage and replication : Unexplored
- Consensus and consistency : Unexplored
- Partitioning and sharding : Aware
- Batch processing : Unexplored
- Stream processing : Unexplored
- Lakehouse and table formats : Aware
- Data pipelines and orchestration : Unexplored
- Training data and feature stores : Working
Systems
Operating systems and runtime
- Processes and scheduling : Aware
- Virtual memory : Aware
- Concurrency and synchronization : Aware
- Storage and I/O : Aware
- Drivers and the HW/SW boundary : Unexplored
- Virtualization and containers : Unexplored
- Cluster scheduling : Unexplored
Compilers and kernels
- Front-end and IR : Unexplored
- Optimization passes : Unexplored
- Code generation and register allocation : Unexplored
- Linking, ABI and runtime : Unexplored
- GPU programming model : Aware
- Kernel optimization : Aware
- ML compilers and graph optimization : Aware
Computer architecture
- ISA and CPU microarchitecture : Aware
- Memory hierarchy and caches : Aware
- Coherence and memory model : Unexplored
- SIMD and vector processing : Aware
- GPU architecture : Aware
- Domain-specific accelerators : Aware
- Interconnect and topology : Aware
- Performance modeling : Aware
Chip design
Digital design and verification
- SoC architecture and PPA : Aware
- RTL design : Aware
- Functional and formal verification : Aware
- Logic synthesis : Aware
- Memory and IP integration : Aware
- Design for test : Aware
- Low-power design : Unexplored
Physical implementation and signoff
- Floorplanning and placement : Aware
- Clock tree synthesis : Aware
- Routing : Aware
- Parasitic extraction : Aware
- Static timing analysis : Aware
- Power, IR drop and EM : Aware
- Physical verification : Aware
- Signoff and tape-out : Aware
Analog, mixed-signal and RF
- Analog building blocks : Aware
- Data converters : Aware
- Clocking and PLL : Aware
- Power management : Unexplored
- RF front-end : Unexplored
- SerDes and signal integrity : Aware
- Schematic and custom layout : Aware
Silicon
Device physics and modeling
- Semiconductor physics and transport : Expert
- MOSFET electrostatics and scaling : Expert
- Device architectures : Expert
- Memory and emerging devices : Expert
- Power and RF devices : Aware
- Reliability physics : Expert
- TCAD and device simulation : Expert
- Compact modeling and extraction : Working
- DTCO : Working
Process and manufacturing
- Thin films and deposition : Expert
- Lithography and patterning : Working
- Etch and planarization : Working
- Doping and implantation : Working
- FEOL/MOL/BEOL integration : Working
- Metrology and process control : Working
- Yield and defect analysis : Working
- PDK and design rules : Aware
- Packaging, assembly and test : Aware